`timescale 1ns/1ns

module arithmetic_shift_tb;
    reg signed [7:0] i_a = 8'sb0011_0111;
    reg signed [2:0] i_bit = 0;
    
    wire signed [7:0] o_sll,
                    o_srl,
                    o_asl,
                    o_asr;

    initial begin
        $dumpfile("output/arithmetic_shift_tb.vcd");
        $dumpvars(0, arithmetic_shift_tb);
    end

    
    initial while(i_bit<7) #20 i_bit = i_bit + 1'b1;
    initial #160 $stop;
    
    arithmetic_shift arithmetic_shift_inst(
    .iA   (i_a),
    .iBit (i_bit),    
    .oSLL (o_sll),    
    .oSRL (o_srl),
    .oASL (o_asl),
    .oASR (o_asr)   
    );
 
endmodule